Tutorial: The HERMES design flow: an FPGA synthesis flow targeting space applications

Venue: 02.016, Ashby Building, QUB.

Organizers: Fabrizio Ferrandi (Politecnico di Milano, Italy), Alp Kilic (Nanoxplore, France), Michele Fiorito (Politecnico di Milano, Italy), Claudio Barone (Politecnico di Milano, Italy)

Abstract: Rad-hard FPGAs today are a crucial processing element in space application performance, and they see increased adoption in future aerospace and avionic markets. FPGAs have traditionally been programmed with hardware description languages, requiring significant engineering efforts and long development times. Today, the availability of new high-level synthesis (HLS) tools to generate accelerators starting from high-level specifications provides easier access to FPGAs and preserves programmer productivity. This tutorial will present tools and technology developed within ESA, CNES, and EU funding efforts (BRAVE, VEGAS, OPERA, DAHLIA, and HERMES projects) to address the end-to-end design flow for these critical applications. The tutorial aims to provide a systematic overview of the current state, opportunities, and challenges in using reconfigurable computing to accelerate space-oriented applications and present an open-source, publicly available, research-driven toolchain combined with a commercial RTL synthesis tool developed for this specific domain. The Hands-on presentations of the toolchain for the automatic generation of FPGA accelerators in harsh environments will provide attendees with all the information necessary to be productive with an integrated framework using the NxMap commercial RTL synthesis tool and the open-source high-level synthesis tool Bambu.