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AWARDS

FPL Best Paper Awards

The International Conference on Field-Programmable Logic and Applications currently recognizes three main awards:

Michal Servít
Memorial Award (MS)

Presented to the most outstanding paper in the area of design algorithms, methods, and CAD tools for FPGAs and self-aware systems.

Stamatis Vassiliadis
Memorial Award (SV)

Presented to the most outstanding paper in the area of architecture and applications.

FPL Community
Award (CO)

Presented to individuals who have made a significant contribution to the community by providing some material or knowledge in an open format that benefits the rest of the community.

The awards listed below have been presented at FPL over the years.

FPL 2025 (Leiden, The Netherlands)

MS
From Errors to Solutions: LLM-Powered Command Scripting for FPGA CAD Tools
Mohamed A. Elgammal and Vaughn Betz
SV
Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage
Xilai Dai, Junius Pun, Grace Zgheib, Mahesh Iyer, Andrew Boutros, Vaughn Betz, and Mohamed Abdelfattah
CO
Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research
Aman Arora, Andrew Boutros, Daniel Rauch, Aishwarya Rajen, Aatman Borda, Seyed Alireza Damghani, Samidh Mehta, Sangram Kate, Pragnesh Patel, Kenneth B. Kent, Vaughn Betz, and Lizy K. John

FPL 2024 (Turin, Italy)

MS
DynaRapid: Fast-Tracking from C to Routed Circuits
Andrea Guerrieri, Srijeet Guha, Chris Lavin, Eddie Hung, Lana Josipović, and Paolo Ienne
SV
SERI: High-Throughput Streaming Acceleration of Electron Repulsion Integral Computation in Quantum Chemistry Using HBM-Based FPGAs
Philip Stachura, Guanyu Li, Xin Wu, Christian Plessl, and Zhenman Fang
CO
Artifact Evaluation Initiative
Miriam Leeser and Suhaib Fahmy

FPL 2023 (Gothenburg, Sweden)

MS
Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis
Robert Szafarczyk, Syed Waqar Nabi, and Wim Vanderbauwhede
SV
Co-Visu: A Video Super-Resolution Accelerator Exploiting Codec Information Reuse
Haishuang Fan, Jingya Wu, Wenyan Lu, Xiaowei Li, and Guihai Yan
CO
GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization
Stefan Abi-Karam and Cong Hao

FPL 2022 (Belfast, United Kingdom)

MS
Bitfiltrator: A General Approach for Reverse-Engineering Xilinx Bitstream Format
Sahand Kashani, Mahyar Emami, and James R. Larus
SV
DeLiBA: An Open-Source Hardware/Software Framework for the Development of Linux Block I/O Accelerators
Babar Khan, Carsten Heinz, and Andreas Koch

FPL 2021 (Virtual Conference)

MS
Turning Pathfinder Upside-Down: Exploring FPGA Switch-Blocks by Negotiating Switch Presence
Stefan Nikolić and Paolo Ienne
SV
Eciton: Very Low-Power LSTM Neural Network Accelerator for Predictive Maintenance at the Edge
Jeffrey Chen, Sehwan Hong, Warrick He, Jinyeong Moon, and Sang-Woo Jun
CO
FGPU: An SIMT Architecture for FPGAs
Muhammed Al Kadi, Benedikt Janssen, and Michael Hübner

FPL 2020 (Virtual Conference)

MS
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths
Stefan Nikolić, Grace Zgheib, and Paolo Ienne
SV
LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications
Yaman Umuroglu, Yash Akhauri, Nicholas J. Fraser, and Michaela Blott

FPL 2019 (Barcelona, Spain)

MS
A Deep Learning Framework to Predict Routability for FPGA Circuit Placement
Abeer Alhyari, Ahmed Shamli, Ziad Abuwaimer, Shawki Areibi, and Gary Grewal
SV
Characterizing Power Distribution Attacks in Multi-User FPGA Environments
George Provelengios, Daniel Holcomb, and Russell Tessier

FPL 2018 (Dublin, Ireland)

MS
Machine-Learning Based Congestion Estimation for Modern FPGAs
Dani Maarouf, Abeer Alhyari, Ziad Abuowaimer, Timothy Martin, Andrew Gunter, Gary Grewal, Shawki Areibi, and Anthony Vannelli
SV
Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs
Andrew Boutros, Sadegh Yazdanshenas, and Vaughn Betz

FPL 2017 (Ghent, Belgium)

MS
Voltage Drop-Based Fault Attacks on FPGAs Using Valid Bitstreams
Dennis R. E. Gnad, Fabian Oboril, and Mehdi B. Tahoori
SV
Automated Generation of Banked Memory Architectures in the High-Level Synthesis of Multi-Threaded Software
Yu Ting Chen and Jason H. Anderson
CO
FloPoCo: Parameterized Floating-Point Core Generator
Florent De Dinechin

FPL 2016 (Lausanne, Switzerland)

MS
An Evaluation on the Accuracy of the Minimum Width Transistor Area Models in Ranking the Actual Layout Area of FPGA Architectures
Farheen Fatima Khan and Andy Ye
SV
An Investigation into a Circuit Based Supply Chain Analyzer for FPGAs
Jacob Couch and John Arkoian
CO
JetStream: An Open-Source High-Performance PCI Express 3 Streaming Library for FPGA-To-Host and FPGA-To-FPGA Communication
Malte Vesper, Dirk Koch, Kizheppatt Vipin, and Suhaib A. Fahmy

FPL 2015 (London, United Kingdom)

MS
Hoplite: Building Austere Overlay NoCs for FPGAs
Nachiket Kapre and Jan Gray
SV
CoRAM++: Supporting Data Structure-Specific Memory Interfaces for FPGA Computing
Gabriel Weisz and James C. Hoe
CO
Placement and Routing Frameworks for FPGA Research
Vaughn Betz

FPL 2014 (Munich, Germany)

MS
Hardware Accelerated Novel Optical De Novo Assembly for Large-Scale Genomes
Pingfan Meng, Matthew Jacobsen, Motoki Kimura, Vladimir Dergachev, Thomas Anantharaman, Michael Requa, and Ryan Kastner
CO
LegUp High Level Synthesis Framework
Jason H. Anderson and Stephen Brown

FPL 2013 (Porto, Portugal)

MS
A Run-Time Graph-Based Polynomial Placement and Routing Algorithm for Virtual FPGAs
R. Ferreira, L. Rocha, A. Santos, J. Nacif, Stephan Wong, and Luigi Carro
SV
The Power of Communication: Energy-Efficient NoCs for FPGAs
Mohamed S. Abdelfattah and Vaughn Betz
CO
RIFFA 2.0: A Reusable Integration Framework for FPGA Accelerators
Matthew Jacobsen and Ryan Kastner

FPL 2012 (Oslo, Norway)

MS
Correctly Rounded Floating-Point Division for DSP-Enabled FPGAs
Bogdan Pasca
SV
Automatically Exploiting Regularity in Applications to Reduce Reconfiguration Memory Requirements
Fatma Abouelella, Karel Bruneel, and Dirk Stroobandt
CO
A High Performance, Open Source SATA2 Core
Ashwin A. Mendon, Bin Huang, and Ron Sass

FPL 2011 (Crete, Greece)

CO
RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs
Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, and Brad L. Hutchings

FPL 2010 (Milan, Italy)

MS
Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains
Thomas B. Preusser and Rainer G. Spallek
SV
FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers
David B. Thomas and Wayne Luk
CO
ATHENa - Automated Tool for Hardware Evaluation: Toward Fair and Comprehensive Benchmarking of Cryptographic Hardware Using FPGAs
Kris Gaj, Jens-Peter Kaps, Venkata Amirineni, Marcin Rogawski, Ekawat Homsirikamol, and Benjamin Y. Brewster

FPL 2009 (Prague, Czech Republic)

MS
Exploiting Fast Carry-Chains of FPGAs for Designing Compressor Trees
Hadi Parandeh-Afshar, Philip Brisk, and Paolo Ienne

FPL 2008 (Heidelberg, Germany)

SV
Rapid Estimation of Power Consumption for Hybrid FPGAs
Chun Hok Ho, Philip H.W. Leong, Wayne Luk, and Steven J.E. Wilton

FPL 2007 (Amsterdam, Netherlands)

SV
Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications
Chun Hok Ho, Chi Wai Yu, Philip H.W. Leong, Wayne Luk, and Steven J.E. Wilton

FPL 2006 (Madrid, Spain)

 
Multi-Layer Floorplanning on a Sequence of Reconfigurable Designs
Love Singhal and Elaheh Bozorgzadeh
Altera Award
Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays
Scott Y.L. Chin, Clarence S.P. Lee, and Steven J.E. Wilton (Altera Award on FPGA Architectures)
Xilinx Award
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Allan Carroll and Carl Ebeling (Xilinx Award on FPGA Technology)

More about the Awards

Michal Z. Servít was the General Chair of FPL 1994 (Prague, Czech Republic), which at the time was the largest FPL conference ever held. He was an Associate Professor in the Faculty of Electrical Engineering at the Czech Technical University in Prague. Michal Servít attended FPL regularly and served the conference community for many years as a reviewer, a member of the Program Committee, and a member of the Steering Committee. He passed away following a heart attack during a vacation in Austria on 5th December 1997. The community remembers him as a cooperative and highly competent colleague, full of good ideas and deeply committed to the organization of FPL. The first Michal Servít Memorial Award was organized by Stephen Guccione, following an idea proposed by John Schewel, and was first presented at FPL 2009 (Prague, Czech Republic).

Stamatis Vassiliadis (IEEE Fellow, ACM Fellow, and member of the Royal Netherlands Academy of Arts and Sciences) was a Professor at Delft University of Technology and an outstanding computer scientist. He was also the founder of the SAMOS conference, established in 2001. Stamatis Vassiliadis was deeply involved in the organization of many scientific conferences and served as General Chair of FPL 2007 (Amsterdam, The Netherlands). When he passed away much too early on 7th April 2007, the community lost one of its most skilled and inspiring members.

The FPL Community Award was introduced at FPL 2010 (Milan, Italy) by the conference organizers Fabrizio Ferrandi, Marco D. Santambrogio, and Jari Nurmi.

Historical information on the FPL awards is courtesy of the ACM/SIGDA Technical Committee on FPGAs and Reconfigurable Computing .